FPGA Image Decompression
From compressed image data to a reconstructed VGA image, all in hardware.
FPGADigital hardwareSystemVerilog
A hardware image-decompression pipeline that receives compressed data over UART, stores it in SRAM, processes it on the FPGA, and reconstructs the result through VGA output.
Architecture
Compressed image data arrives over UART and is written into SRAM. Decompression logic on the FPGA reads it back, reconstructs the image, and the finished frame is drawn to a monitor through the VGA output.
Stack
- Hardware
- FPGASRAMUARTVGA
- Language
- SystemVerilog
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